Silicon-on-insulator (SOI) technology is becoming of increasing importance in the field of integrated circuits. SOI technology deals with the formation of transistors in a layer of semiconductor material which overlies an insulating layer; the most common embodiment of SOI structures is a single crystal layer of silicon which overlies a layer of silicon dioxide. High performance and high density integrated circuits are achievable using SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductor. For example, for an MOS transistor formed in bulk, parasitic capacitance is present at the junction between the source/drain regions and the underlying substrate, and the possibility of breakdown of the junction between source/drain regions and the substrate region also exists. A further example of parasitic elements are present for CMOS technology in bulk, where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can give rise to latch-up problems. Since SOI structures significantly alleviate the parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well-suited for high performance and high density integrated circuits.
It should be noted that a similar technology to SOI is the silicon-on-sapphire (SOS) technology, which provides similar benefits as those discussed relative to SOI technology above. It should be noted that the invention to be disclosed herein is applicable to SOS structures, as well.
The underlying insulator film in an SOI structure presents certain problems relative to the transistor characteristics, however. In bulk transistors, electrical connection is easily made via the substrate to the body node of an MOS transistor. The relatively fixed bias of the body node provides for a stable threshold voltage relative to the drain-to-source voltage. However, conventional SOI transistors have the body node (i.e., the undepleted volume within the body region) electrically floating, as the body node is isolated from the substrate by the underlying insulator film. Under sufficient drain-to-source bias (even, in some cases, with zero gate bias), impact ionization can generate electron-hole pairs near the drain which, due to the majority carriers traveling to the body node while the minority carriers travel to the drain, cause a voltage differential between the body node and the source of the transistor. This voltage differential lowers the effective threshold voltage and increases the drain current, resulting in the well known "kink" in the drain current-voltage characteristic.
Furthermore, the SOI transistor includes a parasitic "back channel" transistor, with the substrate as the gate and the insulator film underlying the transistor as the gate dielectric. This back channel may provide a drain-source leakage path along the body near the interface with the buried insulator. In addition, the dielectrically isolated body node allows capacitive coupling between the body node and the gate, and diode coupling between the body node and the source and drain, to bias the body node and thus affect the threshold voltage. Each of these factors can contribute to undesirable performance shifts in the transistor relative to design, as well as to increased instability of the transistor operating characteristics.
It is therefore useful to provide electrical bias to the body node of a transistor. A useful body node bias, as in the bulk case, is to ohmically connect the body node to the source of the MOS transistor. This requires that the source node of the transistor be specified, and connection made thereto from the body node of the transistor. Prior methods for body-to-source node connection require specification of the mesa regions on the sides of the gate as drain and source relatively early in the fabrication process. An example of such a method is described in copending application Ser. No. 150,799 filed Feb. 1, 1988 and assigned to Texas Instruments Incorporated, where the source is defined by dedicating a portion of the mesa adjacent to the gate to receive an implant of the same conductivity type as the body, and connecting this dedicated portion to the source via a refractory metal silicide.
It is preferable, of course, that such connection to the body node of an SOI transistor occupy as little surface area as possible. It is especially preferable that such connection not occupy a portion of the source region which is adjacent to the gate, so that the effective channel width of the transistor is not reduced in order to provide such connection.
It is therefore an object of this invention to provide an insulated-gate field effect transistor formed in a semiconductor region overlying an insulator, having a buried source-to-body node connection, so that surface area of the transistor is not required for such connection.
It is another object of this invention to provide such a transistor which provides such connection along the full length of the body node to reduce the distance of travel for impact ionization current, thereby minimizing localized potential drift of the body node.
It is another object of this invention to provide such a transistor having such connection without reduction in the effective channel width of the transistor.
It has further been discovered that the back-channel leakage transistor described hereinabove can be reduced by the provision of a heavily doped region of opposite conductivity type from the drain at the interface of the silicon and the underlying insulator. Such a region will not impact the true MOS current desired at the upper surface (i.e., controlled by the gate), but will provide a reverse-biased junction at back-channel, reducing drain-to-source leakage thereat. The provision of such a region accordingly increases the tolerance of the transistor to ionizing radiation, since such ionizing radiation can lower the threshold of the back-channel device via charge trapping at the lower interface.
It has further been discovered that, in many SOI technologies, the silicon film overlying the insulating layer is prone to have a number of dislocation and twinning defects, such defects being more highly concentrated near the interface with the underlying insulating layer. During the drive-in of the dopant forming the source and drain regions in a typical SOI transistor, the source and drain dopant can diffuse more rapidly in the portion of the silicon film having such defects. Such enhanced diffusion can create drain-to-source leakage, and in the extreme case of such diffusion, the source and drain may be connected together. Provision of a heavily doped region of opposite conductivity type below the source and near the insulating layer interface can reduce the leakage from such enhanced diffusion both by removing the diffusion dopant from the source (i.e., the dopant can diffuse only from the drain side), as well as providing a reverse-biased junction between drain and source in the event enhanced diffusion from the drain reaches all the way under the gate.
It is therefore an object of this invention to provide a transistor having body-to-source node connection formed by a buried region, so that a reverse-biased junction is provided between the drain and the connection at the interface of the semiconductor to the underlying insulator film.
It is therefore a further object of this invention to provide such a connection which reduces drain-to-source leakage due to enhanced diffusion effects in an SOI transistor.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to this specification and the accompanying drawings.